This present invention relates generally to spatial light modulators. More particularly, the invention relates to a method and apparatus for providing control circuitry for actuation of mirrors in a spatial light modulator. Merely by way of example, the invention has been applied to a design of addressing circuitry suitable for driving electrodes associated with micro-mirrors in a spatial light modulator used in a display application. The method and apparatus can be applied to spatial light modulators as well as other devices, for example, micro-electromechanical sensors, detectors, and displays.
Spatial light modulators (SLMs) have numerous applications in the areas of optical information processing, projection displays, video and graphics monitors, televisions, and electrophotographic printing. Reflective SLMs are devices that modulate incident light in a spatial pattern to reflect an image corresponding to an electrical or optical input. The incident light may be modulated in phase, intensity, polarization, or deflection direction. A reflective SLM is typically comprised of an area or two-dimensional array of addressable picture elements (pixels) capable of reflecting incident light.
Some conventional SLMs utilize array designs that include an array of micro-mirrors with a set of electrodes and a memory array positioned underneath each of the micro-mirrors. For display applications, the micro-mirrors are generally fabricated using semiconductor processing techniques to provide devices with dimensions on the order of 15 μm×15 μm or smaller. Using such small mirrors enables display applications to use SLMs in applications characterized by increased image resolution for a given display size. Merely by way of example, HDTV systems, with a resolution of 1,080 scan lines×1,920 pixels/line, are currently available to consumers.
In some applications, the memory array associated with an electrode is fabricated using DRAM memory cells. DRAM cells provide benefits in some SLM applications including device sizes appropriate to the micro-mirror pixel size discussed above. However, DRAM cells leak charge during operation, resulting in the need to recharge the DRAM cells to the appropriate electrode voltage on a periodic basis. Other applications utilize SRAM memory cells as electrode drivers, such as a six transistor SRAM memory element.
FIG. 1 is a simplified schematic illustration of a conventional six transistor (6T) SRAM memory element. As illustrated in FIG. 1, the gates of PMOS transistor 114 and NMOS transistor 116 are coupled and are connected to node 120. The gates of PMOS transistor 110 and NMOS transistor 112 are coupled and are connected to node 122. In general, node 120 is connected to a first terminal and node 120 is connected to a second terminal and the voltages are the two terminals are complementary. Node 120 is connected to an electrode E in FIG. 1 and node 122 is connected to an electrode with an opposite polarity (Ē).
The bit line with signal B is connected to the drain/source of NMOS transistor 132 and the bit-bar line with signal B is connected to the drain/source of NMOS transistor 134. The gates of transistors 132 and 134 are connected to the wordline (WL). As will be evident to one of skill in the art, prior to writing operations, the bit line B and the bit-bar B lines are precharged high. To write a “1” value to node 120, the bit-bar B line is pulled to ground (low). Alternatively, to write a “0” value to node 129, the bit line B is pulled to ground. Thus, writing in the conventional six transistor SRAM illustrated in FIG. 1 is performed by precharging both the bit line and the bit-bar line to high and then pulling a selected line (B or B) to ground.
In the memory element illustrated in FIG. 1, the transistor strength, which depends on the transistor size, is selected so that during write operations, a “0” on the bit line will overpower transistor 110 or 114 during write. Thus, the word line transistor 132/134 is at least 1.5 times the size of PMOS transistors 110/114. At the same time, the NMOS transistors 112/116 must be able to pull the bit line down during read operations, placing the constraint on NMOS transistors 112/116 to be 1.5 to 2 times the size of the word line transistors 132/134. Thus, the transistor sizing for the conventional cell for proper read and write operations is: M110,114<M132,134<M112,116. In the cell illustrated in FIG. 1, the sizing is {M110,114=1×}<{M132,134=1.5×}<{M112,116=3×}.
One option for increasing the number of micro-mirrors in an array is to add additional micro-mirrors to the array. However, additional micro-mirrors of a conventional size increase the silicon real estate used to fabricate the array. Another option is to add additional micro-mirrors while decreasing the size of the individual micro-mirrors, thereby maintaining a generally constant array dimension size. As the size of the micro-mirrors is decreased, the dimensions of the memory cells and electrodes associated with each mirror are generally decreased. Using conventional 6T SRAM designs, the size limitations on the transistor size ratios drives the footprint requirement, resulting in limitations on the ability of a designer to reduce the size of the SRAM cells to support the fabrication of smaller micro-mirrors in high resolution display applications. Thus, there is a need in the art for a spatial light modulator with an improved memory cell architecture.